Tuyển Design Engineer Thu Nhập Thoả Thuận Toàn Thời Gian Tại Hà Nội

As an ASIC Physical Design engineer, you will be responsible for all aspects of PnR, working with customer for technical related issue and input/output requirement, helping construct/modify design flow, physical verification, and timing closure.
Responsible for 1 block or multiple blocks in the project from floorplan to tape-out. Responsible for physical verification, signal integrity, power integrity, timing closure. Develop and maintain methodology and flows related to PnR. Analyze reports and utilize scripting techniques to develop insights and drive rapid timing closure. Communicate with customers and others team for technical related issue and input/output requirement
Responsible for 1 block or multiple blocks in the project from floorplan to tape-out.
Responsible for physical verification, signal integrity, power integrity, timing closure.
Develop and maintain methodology and flows related to PnR.
Analyze reports and utilize scripting techniques to develop insights and drive rapid timing closure.
Communicate with customers and others team for technical related issue and input/output requirement

At least 3 years hands-on experience in ASIC physical design including floorplan, power planning, placement, clock tree synthesis, routing, timing, and signal integrity. Has knowledge of the full design cycle from RTL to GDSII, including chip level. Familiarity with all aspects of PnR of high-performance, mixed-signal SoCs in advanced process technology nodes (28nm and below). Experience on Synopsys or Cadence flow – ICC, Fusion, Innovus, PrimeTime, Formality, Calibre. Proficient in scripting languages (Shell, Tcl and Perl). Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups.
At least 3 years hands-on experience in ASIC physical design including floorplan, power planning, placement, clock tree synthesis, routing, timing, and signal integrity.
Has knowledge of the full design cycle from RTL to GDSII, including chip level.
Familiarity with all aspects of PnR of high-performance, mixed-signal SoCs in advanced process technology nodes (28nm and below).
Experience on Synopsys or Cadence flow – ICC, Fusion, Innovus, PrimeTime, Formality, Calibre.
Proficient in scripting languages (Shell, Tcl and Perl).
Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups.
Nice to have:
Good knowledge in digital design techniques and the state-of-the-art physical design methods. Solid fundamentals in IC design flow and ASIC concepts.
Good knowledge in digital design techniques and the state-of-the-art physical design methods.
Solid fundamentals in IC design flow and ASIC concepts.

Attractive salary. Performance based award. Salary: Very competitive. “FPT care” health insurance provided by PJICO and is exclusive for FPT employees. Have a chance to go Onsite short-term or long-term. Young and dynamic working environment. Continuous development of hard and soft skills through work and professional training. Opportunity to approach newest technology trends. Exciting leisure: sport and art events (football club, family day...). Company’s labor policy completely pursuant to Vietnamese labor legislation plus other benefits offered by the company (Company trip, Holiday, etc.).
Attractive salary. Performance based award.
Salary: Very competitive.
“FPT care” health insurance provided by PJICO and is exclusive for FPT employees.
Have a chance to go Onsite short-term or long-term.
Young and dynamic working environment.
Continuous development of hard and soft skills through work and professional training.
Opportunity to approach newest technology trends.
Exciting leisure: sport and art events (football club, family day...).
Company’s labor policy completely pursuant to Vietnamese labor legislation plus other benefits offered by the company (Company trip, Holiday, etc.).